1. Technical Field
The disclosure herein relates to a semiconductor memory apparatus, and in particular, to an active driver control circuit for a semiconductor memory apparatus.
2. Related Art
Some conventional semiconductor memory apparatus use a synchronization mode that allows the semiconductor memory apparatus to operate in synchronization with a clock. Such a semiconductor memory apparatus receives an external clock to generate an internal clock. The internal clock is used for the internal operation of the semiconductor memory apparatus. That is, the semiconductor memory apparatus performs an operation to store data and an operation to output stored data in synchronization with the internal clock.
The operation to store data is referred to as a write operation and is performed according to a write command. The operation to output stored data is referred to as a read operation and is performed according to a read command. The read command and the write command can be generated external to the semiconductor memory apparatus.
When the semiconductor memory apparatus performs the read or write operation, a bank is first activated, and then data is stored in or output from the bank. After the read or write information the semiconductor memory apparatus performs a precharge operation for a next read or write operation.
As a result, the semiconductor memory apparatus operates in synchronization with the internal clock to perform the activation operation, the read or write operation, and the precharge operation. After the activation operation is completed, a conventional semiconductor memory apparatus waits to perform a read or write operation until the read or write command is received. This waiting period is referred to as an active standby mode.
A conventional semiconductor memory apparatus uses a standby driver to reduce power consumption during the active standby mode. But if the read or write command is received during this period, then the semiconductor memory apparatus needs to drive a driver at the level needed for an activation operation. During this time, the driving ability of the standby driver is inferior to that of the active driver.
Generally, an active driver is driven on a rising edge of the internal clock after the read or write command is received. Accordingly, there is a delay between a time when the read or write command is received and a time when the active driver can be driven. As a result of the delay, the semiconductor memory apparatus cannot always perform a normal read or write operation. This mainly affects the write operation, in which more power is consumed than during the read operation.